Box64 Now Provides Initial Support for RVV 1.0, with Up to 300% Performance Boost – Code is Now Open Source and Upstreamed
The Box64 RISC-V backend initially used scalar instructions to emulate MMX, SSE*, and other x86_64 vector extensions, achieving good compatibility with rv64gc. However, since emulating a single vector instruction often requires several dozen scalar instructions, the performance of Box64 suffers significantly when running x86_64 programs that heavily rely on vector instructions.
Recently, engineers and interns from PLCT Lab have introduced initial support for RVV 1.0 in the Box64 RISC-V backend, submitting over 30 related PRs. This new support allows efficient translation of over 100 SSE instructions to RVV instructions.