This Month in PLCT (September 1, 2022)

Jan 1, 0001 · 15 min.

This Month in PLCT: Issue 37 (September 1, 2022) Link to this heading

Preface Link to this heading

At the PLCT lab and the TAISIER team, we had a busy August preparing and hosting the second RISC-V Summit in China. Due to the ongoing pandemic, we have decided to hold the summit remotely, with over 12 sessions held concurrently in different cities in China. We would like to thank everyone for making this year’s summit our largest one yet and a successful example for concurrent sessions in different local venues.

Last month also saw significant growth in our TAISIER. We grew our roster to 20 full-time staff members, began work on a RISC-V port for a distro named OpenAnolis, awarded title to our first LV4 intern, and commenced work with our BJ67 operating system observation project with over 8 interns.

In September, the PLCT lab will experiment with building an > 1,024-node RISC-V cluster. We look forward to working with you in this new project.

  • Successful conclusion to the second RISC-V Summit in China.
  • SpiderMonkey JIT support projected to see end-of-year completion with help from the V8 porting work group. Some baseline code already upstreamed.
  • Graphical interface, Firefox, LibreOffice, etc. now available for OpenAnolis’ RISC-V port.
  • Zhang Xiang (章翔) to work on backporting RISC-V support to OpenJDK8 with a 16-week projected timeframe.

V8 for RISC-V Link to this heading

General updates.

OpenJDK for RV32GC (Shi Ningning [史宁宁]) Link to this heading

  1. Fix some reg num problems https://github.com/openjdk-riscv/jdk11u/pull/464
  2. clean the code in sharedRuntime_riscv32.cpp https://github.com/openjdk-riscv/jdk11u/pull/466
  3. rewrite the long_move() https://github.com/openjdk-riscv/jdk11u/pull/469
  4. Fix the bug of regname https://github.com/openjdk-riscv/jdk11u/pull/471
  5. change the relationship between j_rargx and c_rargx https://github.com/openjdk-riscv/jdk11u/pull/472
  6. Fix the instructions offset in vtableStubs_riscv32.cpp https://github.com/openjdk-riscv/jdk11u/pull/473
  7. Fix the instructs in riscv32.ad
  8. Improve the div system https://github.com/openjdk-riscv/jdk11u/pull/478
  9. Improve the code style of loadUS2L https://github.com/openjdk-riscv/jdk11u/pull/486
  10. Improve the xchg system https://github.com/openjdk-riscv/jdk11u/pull/496
  11. Improve the atomic_add system https://github.com/openjdk-riscv/jdk11u/pull/497

  1. JDK mainline regression testing on SiFive Unmatched.

    • Tier 1-3 tests clean.
    • Need more testing for Tier 4.

  2. Pull requests merged into mainline:

  3. Pull requests approved/under review for mainline:

  4. JBS issues reported:

  5. Sponsored pull requests to mainline:

  6. Commits for the RV64 Loom port:

  7. GHA support for RISC-V (based on Ubuntu 22.04):

OpenJDK Upstreaming (Zhang Dingli [张定立]) Link to this heading

OpenJDK Upstreaming (Cao Gui [曹贵]) Link to this heading

OpenJDK8 Backporting (Zhang Xiang [章翔]) Link to this heading

  1. Build support.
  1. Build fixes.

Clang/LLVM for RISC-V Link to this heading

gollvm Link to this heading

mold Link to this heading

Note: Further testing pending.

GNU Toolchain for RISC-V Link to this heading

AOSP for RISC-V Link to this heading

Arch Linux for RISC-V Link to this heading

Gentoo for RISC-V Link to this heading

Nixpkgs for RISC-V Link to this heading

Firefox (SpiderMonkey) on RV64GCV Link to this heading

With help from the V8 work group.

DynamoRIO RV64GC Enablement Link to this heading

Preliminary support for RV64GC implemented in DynamoRIO, which will now build on RV64GC (no additional feature supported).

Current five-stage road map for DyanmoRIO’s RV64GC support:

  1. Introduce RISC-V platform-specific functions, frameworks, definitions, etc., allowing DynamoRIO to build on RISC-V. (Done)
  2. Setup RISC-V CI for automated compilation and testing. (In Progress)
  3. Refine RISC-V platform-specific functions and definitions, make DynamoRIO’s built-in example tools functional.
  4. Refine RISC-V unit- and feature-tests, setup CI for automated testing and instruments for long-term maintenance.
  5. Continue RISC-V feature enablement for more complex programs, prepare for long-term maintenance.

See https://gist.github.com/bekcpear/7c9e710ee5b674888fcf5e5d8445dc16 for a more detailed to-do list.

OpenCV for RV64GCV Link to this heading

As part of our GSoC 2022 project, we are currently implementing a new Universal Intrinsic backend for RVV (RISC-V Vector), making the existing Universal Intrinsic framework compatible with scalable (variable-length) backends.

Previously, we have already finished implementing the aforementioned changes to the Universal Intrinsic framework. In August, we have implemented all platform-specific Universal Intrinsic functions and introduced respective unit tests and submitted relevant patches to upstream:

  • PR #22353: Add more universal intrinsic implementations for RVV
  • PR #22429: Add remaining universal intrinsic implementations for RVV

As a result, the new Universal Intrinsic backend for RVV not only supports variable register lengths, it also improves performance significantly over the original backend design, which had an issue where it generated redundant Load/Store instructions. As a next step, we plan to optimize hot-spot functions OpenCV’s image processing module and acquire RVV-enabled devices for performance testing.

For more details on this project:

Experimental SIMD in LIBCXX Link to this heading

  • Implemented aligned_tag interfaces.
  • Implemented mask type for 128-bit elements.
  • Fixed ‘&=’ and ‘|=’ operators in the reference class.
  • Fixed implementation for the where expression.
  • Optimized masked operations, using masked_assign and non-masked versions to replace the original scalar implementation.
  • Optimized hmin/hmax implementations by using LLVM’s builtin vector reduction in place of the original scalar implementation.

LuaJIT RV64G porting Link to this heading

Our intern has unfortunated resigned. We are currently in search for a new intern.

gem5 Link to this heading

  • Progression for RVV bring-up.
    • Current draft patch, https://gem5-review.googlesource.com/c/public/gem5/+/59789
    • Introduced support for Vector Integer Extension instructions.
    • Introduced support for Single-Width Floating-Point/Integer Type-Convert instructions.
    • Introduced support for Widening Floating-Point/Integer Type-Convert instructions.
    • Introduced support for Narrowing Floating-Point/Integer Type-Convert instructions.
    • Introduced support for Vector Mask instructions.
    • Introduced support for Vector Narrowing instructions.
    • Introduced support for Vector Single-Width Averaging instructions.
    • Introduced support for Vector Single-Width Fractional Multiply with Rounding and Saturation instructions.
    • Introduced support for Square-Root instructions.
    • Introduced support for Vector Floating-Point Classify instructions.
    • Introduced support for Vector Narrowing Fixed-Point Clip instructions.
    • Introduced support for Vector Register Gather instructions.
    • Fixed various known issues.
  • Others.

Spike Link to this heading

QEMU Link to this heading

Other Support for RISC-V International Link to this heading

Please stay tuned.

SAIL/ACT Link to this heading

Please stay tuned.

OpenArkCompiler Community Link to this heading

Shi Ninging (史宁宁) continues to work on compiling the OpenArkCompiler Weekly, which received the 128th edition.

You may find new weekly editions of the OpenArkCompiler Weekly on Sundays on…

MLIR Link to this heading

Please stay tuned.

Upstream RVV Dialect Proposal Link to this heading

Google’s IREE partner Diego proposed an RFC for a generic Vector Masking Representation in MLIR, https://discourse.llvm.org/t/rfc-vector-masking-representation-in-mlir/64964

References

OSPP Mentorship Link to this heading

Buddy Compiler Link to this heading

Website

buddy-mlir

New features:

  • Add function to Toy DSL examples.
  • Add struct support to Toy DSL examples.
  • Infer operation data type based on its params for Corr2D.
  • Add more VP intrinsic examples.
  • Add the example for dialect interface: BudInlinerInterface.
  • Refactor image traversal with boundary extrapolation for efficient reuse.

buddy-benchmark

New features:

  • Add basic comparision plots function.

Chisel / FIRRTL (CAAT Work Group) Link to this heading

coreboot for riscv Link to this heading

Please stay tuned.

openocd Link to this heading

  • Setting SIZE when using triggers as watchpoints. Currently under deliberation and review.
    • Pull request, #721
    • Upstream issue, #720

opensbi Link to this heading

Submitted various patches to upstream.

  • [PATCH v2 0/5] Set hstatus.GVA for traps going to HS-mode, ref
  • [PATCH v1] lib: sbi_illegal_insn: Fix FENCE.TSO emulation infinite trap loop, ref
  • [PATCH v2 0/5] Add support for T-HEAD C9xx PMU extensions, ref
  • [PATCH v3] lib: utils: serial: Add Cadence UART driver, ref
  • [PATCH v8 00/17] OpenSBI Kconfig Support, ref
  • [PATCH] lib: sbi: Use the official extension name for AIA M-mode CSRs, ref
  • [PATCH] include: Remove sideleg and sedeleg, ref
  • [PATCH 0/7] OpenSBI PMU improvements, ref
  • Documentation fixes for Unmatched PMU.

U-Boot Link to this heading

  • [PATCH] virtio: pci: fix bug of virtio_pci_map_capability, ref

The Aya Theorem Prover Link to this heading

👉View current pull requests here👈

You may find the full list of August changes here.

RISC-V Platform Evaluation Link to this heading

RVLab Link to this heading

  1. Created a frontend for RVLab’s hardware management platform using Vue.js.
  • Learning to make of Vue.js’ parent and child component functionalities - using value passing and function calls in various dialog interfaces.
  • Completed device distribution, device editing, relay listing, new/delete relays, and delete device pages in the hardware management interface.
  • Completed user management, user roles, role listing, new/delete roles, delete user pages.
  • Completed the User Profile interface, as well as a functional Change Password page.
  • Successfully deployed the RVLab hardware management platform locally on a Ubuntu 22.04 system using Dockerfile and docker compose. This platform will be deployed for production in a virtual machine. Due to the fact that the MQTT server was deployed in the RVLab’s internal network, the virtual machine will require both Internet and intranet access.
  • Revised Flask backend code to adapt to the Vue frontend.
  1. RVLab infrastructure provisioning.
  • Installed the latest Debian image on one Unmatched board.

openEuler for RISC-V Link to this heading

See TAISIER’s bi-weekly reports, https://github.com/isrc-cas/tarsier-oerv/

Debian for RISC-V Link to this heading

Now published in a bi-weekly format, please find these reports at the debian-riscv mailing list.